The present invention relates in general to semiconductor devices, and more particularly to transistors fabricated on high density integrated circuits.
There is a continuing demand for higher density integrated circuits with smaller transistor dimensions. For example, the dimensions of future transistors are expected to be scaled down to one hundred nanometers or less, and to be fabricated with gate dielectrics made with high permittivity materials.
However, integrated circuits are subjected to temperatures exceeding one thousand degrees Celsius in order to activate the transistor""s source and drain diffusions. Most if not all high permittivity materials are unable to withstand such high temperatures without degradation. This problem can be avoided by using a sacrificial or dummy gate to align a transistor""s source and drain. The dummy gate typically is formed with polysilicon or silicon dioxide, which can withstand the high temperature activation. After activating the source and drain, the dummy gate is removed and the high permittivity material is deposited to form the gate dielectric.
A dummy gate process has a disadvantage that removing the dummy gate causes extraneous material to be removed as well, which reduces the control over critical transistor dimensions. Moreover, voids often are left, which increases stress in the transistor and degrades the reliability of the integrated circuit.
Hence, there is a need for a structure and method of fabricating a transistor which maintains good control over critical transistor dimensions and which does not leave voids which degrade reliability.